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ADuC7060
Table 58. ADC0ACC MMR Bit Designations
Primary Channel ADC Comparator Threshold Register
Bits
31 to 0
Description
ADC0 32-bit threshold exceeded counter register.
Name:
Address:
ADC0ATH
0xFFFF054C
Table 59. ADC0ATH MMR Bit Designations
Bits Description
Default value:
0x00000000
31 to 0
ADC0 32-bit comparator threshold register of the
Access:
Read and write
accumulator.
Function:
This 32-bit MMR holds the threshold value for
the accumulator comparator of the primary
channel. When the accumulator value in
ADC0ACC exceeds the value in ADC0ATH,
the ADC0ATHEX bit in ADCSTA is set. This
causes an interrupt if the corresponding bit in
ADCMSKI is also enabled.
FAST
OVERRANGE
INTERRUPT
(ADC0OVR)
(READABLE)
ADC0
ADC1
MAIN
ADC
f ADC
16
(READABLE)
f ADC
ADC0ACC
ACCUMULATOR
32
≥
INTERRUPT
(ADC0ATHEX)
ADC0ATH
CLEAR
ADC0RCV
COUNTER
|ABSVAL|
f ADC
ADC0RCR
(DEFAULT = 1)
≥
INTERRUPT
(ADC0RDY)
ADC0TH
≥
f ADC
ADC0THV
UP/DOWN
OPTION: UP/RESET
≥
INTERRUPT
(ADC0THEX)
ADC0THC
Figure 16. Primary ADC Accumulator/Comparator/Counter Block Diagram
Rev. 0 | Page 48 of 100
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